MosChip Technologies unveils multi-lane multi-protocol LR 8G PHY

MosChip Technologies Limited, an Indian semiconductor and system design service company, has unveiled the multi-protocol, long range (LR) 8G SerDes PHY in 28nm.

The multi-lane multi-protocol LR 8G PHY is part of the company’s multi-rate transceiver line-up.

According to MosChip Technologies, the new chipset is designed to handle the increasing demand for small footprint, low power consumption, as well as low latency edge applications.

The fabless semiconductor company said that PHY is fully configurable to either enable or disable programmable lane and for a choice of macros that are pre-configured for 1 to 16 lanes. It includes multiple debug features like parallel and serial loop back.

MosChip Technologies unveils multi-lane multi-protocol LR 8G PHY. Image courtesy of MosChip Technologies Limited.

Venkata Simhadri — MD/ CEO of MosChip Technologies said: “This is a major milestone for MosChip, which highlights our strategic focus to develop niche SerDes PHY IP that is customizable as per customer end applications.

“With the addition of silicon proven LR 8G PHY to our portfolio, we are well positioned to provide both custom/ porting PHY IP services and turn-key mixed-signal ASIC solutions.”

The 8G PHY macro is said to be backward-compatible and can be used in accordance with PCI Genl2 / 2, SATA 1/2 specifications. It comes with a PCIe standard multi-lane interface. As per MosChip Technologies, there is no need for any external passive components, thereby saving space at the system level and pin count at the chip level.

Deliverables for LR 8G PHY macro comprise a comprehensive set of logical and physical views, as well as documentation, which includes a Verilog model as well as a UVM-based verification environment, abstract views, liberty files, netlist, GDS-I and flip chip bump maps.

Albert Vareljian — Chief Architect at MosChip Technologies said: “Our LR 8G PHY is implemented as a self-contained protocol-agnostic Physical Medium Attachment (PMA) IP with a flexible digital Y F on the system side that could be made compatible with the most PCS standard definitions that exist in the industry today.

“PHY is based on our innovative self-tuning architecture and fully adaptive continuous-time equalizer with automatic gain control analog front end (AFE) combined with adaptive multi-tap decision feedback equalization (DFE) to cover channel variations and PVT”.