CEA-Leti and Soitec launch FD-SOI cybersecurity initiative for secure automotive and industrial chips

Semiconductor materials innovator Soitec (EPA: SOI) and French research institute CEA-Leti have unveiled a strategic partnership focused on advancing fully depleted silicon-on-insulator (FD-SOI) technologies to deliver greater cybersecurity resilience in embedded chips. The collaboration aims to position FD-SOI as a foundational cyber-secure substrate, especially for embedded systems in the automotive, industrial IoT, and secure infrastructure sectors.

Under the agreement, both organizations will co-develop and validate enhancements to FD-SOI’s intrinsic protection against physical attacks, including laser fault injection, substrate probing, and side-channel exploits. By leveraging their respective strengths in substrate engineering and circuit-level security research, Soitec and CEA-Leti intend to generate empirical data that strengthens FD-SOI’s relevance in security-critical certification frameworks such as SESIP and Common Criteria.

This move aligns with growing industry demand for chips that deliver both power efficiency and hardware-level protection—an intersection increasingly vital for electronic control units (ECUs), industrial sensors, and mission-critical digital infrastructure.

Why is the Soitec–CEA-Leti partnership significant for the future of embedded chip cybersecurity?

FD-SOI technology is already recognized in the semiconductor community for its ability to support ultra-low-power designs and high energy efficiency. But in recent years, its utility in deterring invasive physical attacks has drawn particular attention in markets where chips must withstand tampering, radiation, and side-channel probing.

CEA-Leti Chief Technology Officer Jean-René Lequepeys stated that this partnership comes at a time when cyber-physical systems—including autonomous vehicles and edge-deployed industrial controllers—are increasingly exposed to hardware-level intrusion attempts. He indicated that the collaboration would build on results from the FAMES Pilot Line and enable demonstrable, reproducible security metrics across FD-SOI substrates and circuits.

Institutional observers see this as a timely strategic move, particularly in Europe, where sovereign chip development and secure-by-design mandates are accelerating due to geopolitical instability and industrial digitalization.

How does FD-SOI provide inherent resistance to physical attacks in chip design?

The FD-SOI architecture is uniquely equipped to address security challenges at the substrate level. Its thin-film silicon structure and buried oxide layer provide electrical isolation between the transistor channel and the bulk substrate. This structure inherently resists many physical attack vectors, such as fault injection and substrate manipulation.

Soitec and CEA-Leti plan to validate these attributes through joint experiments and simulations. Early trials are expected to focus on validating resistance to laser-based fault injection—a common method of altering chip logic without direct contact. The long-term objective is to define a new baseline for trusted semiconductor platforms where security is embedded directly into the physical stack.

FD-SOI also offers benefits for design-stage security countermeasures. These include enabling fault detection circuits, secure domain isolation, and efficient integration of physical unclonable functions (PUFs) used for chip fingerprinting and anti-cloning purposes.

Which markets and applications are driving the need for FD-SOI-based secure chips?

The industrial shift toward automation, electrification, and decentralized intelligence is amplifying the need for embedded systems that are not only efficient but intrinsically trustworthy. In the automotive sector, for example, ECUs and domain controllers must meet stringent safety and security standards under ISO 26262 and WP.29 cybersecurity frameworks. Chips built on FD-SOI could offer a secure substrate for such functions without imposing excessive power or thermal constraints.

In industrial IoT, devices deployed in remote or unsupervised environments often lack physical protection. Here, FD-SOI’s tamper-resistance could reduce the risk of localized compromise, while its energy efficiency supports long battery life—an important factor in distributed sensor networks.

Both Soitec and CEA-Leti emphasized that this initiative is designed to support certification pathways in high-assurance environments. The collaboration could ultimately enable chipmakers and Tier-1 suppliers to meet regulatory requirements more efficiently while embedding long-term cyber-resilience.

What are the goals of the “cyber-substrate” concept and how might it evolve beyond FD-SOI?

The partnership is not limited to leveraging existing FD-SOI advantages—it also aims to push the boundaries of secure substrate design. According to Soitec’s Senior Executive Vice President of Innovation, Christophe Maleville, the collaboration sets a long-term trajectory toward developing an advanced “cyber-substrate” that incorporates built-in anti-tamper features, hardware entropy generators, and real-time response capabilities.

These next-generation substrates may include hardened backside interfaces and localized shielding to resist backside and invasive probing. Other design directions include integrating sensor nodes that detect environmental anomalies—such as voltage, light, or magnetic field changes—and trigger chip-level mitigation protocols.

Analysts believe this could position Soitec and CEA-Leti at the forefront of a new category of secure silicon platforms, especially as AI, robotics, and decentralized networks continue to drive demand for edge-resident computing with verifiable trust.

What role does GlobalFoundries play in the execution of this FD-SOI cybersecurity roadmap?

While the partnership between Soitec and CEA-Leti centers on R&D and substrate innovation, manufacturing capabilities will be delivered through GlobalFoundries—an established partner in the FD-SOI ecosystem. GlobalFoundries’ 22FDX platform has been widely adopted for automotive and low-power applications, and its foundry services are expected to provide scale and consistency for security-enhanced FD-SOI designs.

This vertically integrated approach—combining substrate innovation, academic R&D, and industrial fabrication—will be crucial for meeting both performance and certification requirements. The collaboration also signals a deepening alignment between European semiconductor innovation and global manufacturing resources, particularly as regional chip strategies emphasize design sovereignty without compromising scale.

How does this partnership reflect broader trends in secure semiconductor development?

The Soitec–CEA-Leti partnership reflects a maturing recognition that chip-level security cannot be an afterthought. As the semiconductor supply chain globalizes and threat vectors become more sophisticated, building security from the substrate upward is becoming a critical differentiator.

Institutional investors tracking semiconductor IP, edge AI, and automotive chipmakers are increasingly evaluating platforms based on their embedded trust properties. Several are reportedly exploring investment in IP-rich players that offer certification-ready architectures and partnerships with sovereign R&D bodies.

Analysts expect that FD-SOI’s security profile—if backed by quantitative, third-party validation—could help expand its adoption in high-assurance applications beyond current mobility and IoT segments. These include digital ID authentication, defense-grade sensors, and secure boot architectures for field-deployed devices.

What is the long-term business and policy outlook for FD-SOI in secure silicon markets?

With governments prioritizing chip security under national digital sovereignty and AI safety strategies, foundational technologies like FD-SOI could see rising demand across public and private sectors. In Europe, initiatives such as IPCEI (Important Projects of Common European Interest) on microelectronics are channeling funds toward R&D efforts that align with trusted compute and hardware resilience goals.

Industry insiders suggest that FD-SOI-based secure chips may also be incorporated into future cybersecurity compliance frameworks, making certification-friendly substrates a commercial imperative. Soitec’s positioning in this space—with over 4,000 patents and a strategic emphasis on secure edge computing—suggests that the French semiconductor firm is preparing to play a central role in that evolution.

As the cybersecurity landscape evolves toward real-time resilience and chip-native trust enforcement, the strategic alignment between Soitec and CEA-Leti is poised to define a new reference point for hardware-rooted security in embedded systems.