The Semiconductor Manufacturing and Advanced Research with Twins USA Institute (SMART USA), a federally supported semiconductor innovation consortium, has launched its first competitive solicitation targeting digital twin technologies. The program, announced on June 11, 2025, allocates up to USD 50 million in blended federal and private-sector funding to projects aimed at improving the efficiency, reliability, and scalability of semiconductor manufacturing in the United States.
This funding opportunity is part of SMART USA’s broader strategic vision to bolster U.S. chipmaking competitiveness through cutting-edge digital modeling systems. Projects selected for funding will address key bottlenecks in fabrication and packaging through collaborative approaches that integrate industry, academia, and workforce development.
The institute’s solicitation is supported by the U.S. Department of Commerce’s CHIPS Research and Development Office in conjunction with member co-investments, reinforcing a hybrid funding model that aims to accelerate advanced technology commercialization and skill-building initiatives.
What is SMART USA and what are its goals for digital twin technology?
Founded as a part of the CHIPS and Science Act implementation, SMART USA is one of several National Semiconductor Technology Centers operating with federal backing to revitalize domestic chip manufacturing. Based in Durham, North Carolina, the institute focuses specifically on the deployment of digital twin systems—sophisticated virtual replicas of physical semiconductor processes that enable real-time monitoring, simulation, and optimization.
SMART USA’s leadership has articulated a five-year vision that includes reducing semiconductor manufacturing costs by over 35%, accelerating process development by 30%, and establishing production-grade digital twins that span the entire value chain—from wafer fabrication to packaging. This first funding round marks the initial step in operationalizing that agenda.
What is the scope of the $50 million funding opportunity for digital twins?
The June 2025 solicitation invites proposals from SMART USA members, requiring teams to consist of at least three separate organizations. The range of available funding per project spans from USD 500,000 to USD 20 million, with a project duration limit of 24 months. SMART USA emphasized that both technical deliverables and educational outputs are mandatory components of all funded proposals.
The technical development categories include: optimization of semiconductor manufacturing through digital twins, digital twin co-design for advanced packaging, and validation platforms for ensuring interoperability across hardware and software stacks. On the education front, proposals must address community college access and the development of scalable training libraries.
All funded projects will contribute educational content to SMART USA’s digital marketplace—ensuring that training materials and process knowledge are accessible to future workforce pipelines. This dual mandate reflects the institute’s recognition that sustainable innovation must go hand-in-hand with skill development.
How does SMART USA plan to foster collaboration among industry and academia?
A cornerstone of SMART USA’s funding architecture is its insistence on cross-organizational collaboration. Applicants are required to assemble consortia that may include semiconductor manufacturers, equipment suppliers, design software vendors, academic researchers, and workforce training bodies.
Christopher Ritter, Chief Digital Officer at SMART USA, emphasized that this structural requirement helps build a “network of digital twin capabilities” rather than isolated project outcomes. Ritter noted that by encouraging interoperability and shared research across the value chain, the initiative aims to deliver systemic improvements to U.S. chip production resilience.
This emphasis on coordination also reflects growing federal interest in horizontally integrated innovation ecosystems, as opposed to vertically siloed R&D pipelines that may hinder technology diffusion.
What are the expected institutional impacts of this funding initiative?
While SMART USA itself is not publicly traded, the announcement has implications for member companies that span across listed semiconductor fabricators, tooling firms, and digital design software developers. Institutional analysts monitoring the semiconductor value chain view such funding rounds as a signal of increased federal commitment to scaling advanced process capabilities, particularly amid global efforts to reshore chip production and reduce dependency on East Asian supply routes.
Moreover, the inclusion of workforce development as a core deliverable aligns with investor concerns about skilled labor shortages that have already delayed recent fab construction timelines in Arizona and Ohio.
Tymeeka Middleton, Chief Workforce Officer at SMART USA, highlighted that the solicitation will also catalyze next-generation talent development, offering “unprecedented opportunities for collaboration between organizations that might otherwise compete.” This is expected to appeal to institutional stakeholders evaluating long-term labor force readiness across the semiconductor manufacturing ecosystem.
What is the timeline for proposal submissions and project kickoffs?
Organizations interested in submitting proposals must do so by August 11, 2025, at 11:59 PM Eastern Time. SMART USA encourages interested members and potential collaborators to attend the SMART USA Summit in Arlington, Virginia, on June 26–27, 2025, to facilitate teaming discussions and obtain clarification on the solicitation process.
Award notifications are expected by late Q4 2025, with funded projects commencing on January 1, 2026.
The SMART USA solicitation comes amid a broader landscape of semiconductor investment announcements, from the USD 8.5 billion CHIPS Act award to Intel for domestic fabs, to rising venture capital flows into advanced materials and packaging startups. Analysts believe that digital twin technologies, while still maturing, could unlock significant cost reductions and throughput gains, particularly in lithography, etch, and test stages of the manufacturing lifecycle.
What’s next for digital twin innovation in semiconductors?
Industry observers expect additional solicitations from SMART USA in subsequent years as part of its evolving mandate. These could include domain-specific challenges in analog, RF, or heterogeneous integration spaces, as well as funding calls tailored toward small-to-medium enterprises (SMEs) and regional workforce hubs.
Several members of the SMART USA coalition—including global equipment providers and major U.S. chipmakers—are also reportedly working on pilot digital twin deployments aligned with the goals of this solicitation. If successful, these projects could form the backbone of a next-generation semiconductor digital infrastructure.
With federal agencies aiming for a 2030 horizon for U.S. semiconductor self-sufficiency, programs like SMART USA’s digital twin initiative are likely to remain central to national industrial strategy. Analysts expect further policy alignment and follow-on funding mechanisms in the FY2026 CHIPS budget.
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