Marvell bets on 2nm die-to-die interface: Can it solve AI’s power and bandwidth crisis?

How does Marvell’s 64 Gbps bi-directional die-to-die interface change the economics of advanced data center chip design?

Marvell Technology, Inc. (NASDAQ: MRVL) on August 26 announced what it called an industry-first: a 64 Gbps per wire bi-directional die-to-die (D2D) interconnect built on a 2nm process node. The Santa Clara-based data infrastructure semiconductor developer positioned the launch as a breakthrough that will allow chipmakers to dramatically scale bandwidth, performance, and efficiency in next-generation XPUs—accelerated processing units central to artificial intelligence, hyperscale cloud, and advanced data center architectures.

The innovation marks a new phase in Marvell’s push into ultra-advanced process technology. By offering simultaneous two-way connectivity of 32 Gbps per direction on a single wire, the new interface achieves bandwidth density exceeding 30 terabits per second per square millimeter. According to the company, this figure is more than three times the bandwidth density of Universal Chiplet Interconnect Express (UCIe) at equivalent speeds, while reducing compute die area requirements by up to 85 percent compared with conventional implementations.

Why is Marvell positioning this 2nm die-to-die technology as a turning point for AI infrastructure?

The importance of die-to-die interfaces lies in their role as the backbone of multi-die chip architectures, which are increasingly common in high-performance AI accelerators and custom compute designs. As monolithic silicon becomes costlier and more challenging at advanced nodes, the industry has shifted toward chiplets and heterogeneous integration. By optimizing these D2D interconnects, Marvell is effectively tackling one of the most pressing bottlenecks in scaling AI hardware.

A defining feature of Marvell’s 64 Gbps solution is its adaptive power management. The system dynamically adjusts activity based on traffic intensity, reducing interface power consumption by up to 75 percent during normal workloads and as much as 42 percent during peak loads. This is especially critical for hyperscale operators facing ballooning energy bills and sustainability pressures as AI training models and inference workloads grow.

The launch also incorporates reliability-enhancing functions such as redundant lanes and automatic lane repair, which can improve silicon yield and reduce bit error rates. Taken together, Marvell claims the platform is not only higher performing but also more resilient—an attribute of growing importance as AI-driven workloads demand uninterrupted scaling.

How does this technology compare to existing interconnect standards like UCIe?

Marvell’s announcement places it in direct comparison with UCIe, the industry’s dominant open standard for die-to-die connectivity. While UCIe provides a universal framework for multi-die integration, its bandwidth density at comparable speeds lags behind Marvell’s proprietary solution by a factor of three, based on the company’s benchmarks.

The reduced silicon footprint also addresses a core pain point for chipmakers: die area costs at 2nm and 3nm nodes. With compute-intensive designs increasingly modular, the ability to minimize area overhead becomes a competitive differentiator. Analysts noted that by directly addressing die cost and interconnect efficiency, Marvell’s offering could give semiconductor designers more flexibility in custom architectures, particularly in AI accelerators, network processors, and data center CPUs.

What role does power efficiency play in positioning this as a data center-ready technology?

Energy consumption has emerged as a critical limiting factor in AI infrastructure expansion. Training frontier models already requires megawatt-scale compute clusters, and hyperscalers from Microsoft to Google have flagged the rising power draw of AI as both an economic and environmental challenge.

Marvell’s adaptive power management offers an immediate response to this challenge. By scaling back consumption during idle and bursty workloads, the system can substantially lower total cost of ownership. Industry observers suggested that this could resonate with hyperscalers looking to balance AI demand growth with carbon neutrality commitments and grid constraints.

In practice, analysts expect that power-efficient interconnects like Marvell’s will become integral to data center procurement decisions. While raw performance remains crucial, total energy per operation is increasingly scrutinized by institutional investors focused on ESG metrics.

How does this launch fit into Marvell’s broader 2nm roadmap and semiconductor innovation history?

The unveiling continues a multi-year string of technology firsts by Marvell in advanced process nodes. In March 2024, Marvell announced its 2nm platform, becoming the first infrastructure silicon company to publicly claim availability. By March 2025, it had demonstrated working 2nm silicon, followed by the release of a 2nm custom SRAM.

The latest announcement adds interconnect IP to this roadmap, positioning Marvell as a comprehensive solutions provider rather than a niche player. By offering a complete stack—including the D2D PHY, application bridge, link layers, and physical interconnect—the firm aims to accelerate time-to-market for customers while embedding itself deeper into the design of custom XPUs.

Institutional sentiment has generally regarded Marvell as one of the semiconductor firms most aggressively aligned with AI infrastructure. Its positioning in data interconnects, custom compute silicon, and cloud-optimized chips has differentiated it from peers like Broadcom, which dominate networking but remain less exposed to custom AI silicon.

What has been the stock market response and investor sentiment toward Marvell’s 2nm advances?

Marvell Technology’s shares (NASDAQ: MRVL) have been volatile in 2025, reflecting broader semiconductor market swings tied to AI demand, supply chain dynamics, and capital intensity. Ahead of the announcement, the stock had been trading with mixed institutional sentiment: some investors cited strong AI alignment as a growth driver, while others flagged concerns about margin pressure and the capital-heavy nature of keeping pace with 2nm development.

Following the launch, analysts suggested that the unveiling could improve perception of Marvell’s differentiation in interconnects—a segment increasingly recognized as critical to AI economics. While short-term valuation moves depend on quarterly results, long-term sentiment points toward institutional investors maintaining a cautiously optimistic outlook, balancing AI tailwinds against cyclical risks in semiconductors.

Buy-side flows in recent quarters have shown rotation into AI-exposed semiconductor firms, though hedge fund positioning has remained selective. With Marvell establishing technical leadership in die-to-die connectivity, analysts believe it could attract renewed interest, particularly if early design wins for the 64 Gbps interface are confirmed.

What is the future outlook for Marvell as it deepens its exposure to AI-driven infrastructure demand?

Looking ahead, Marvell’s success will hinge on how quickly its new die-to-die IP is adopted in production designs by leading cloud and AI customers. The firm has emphasized time-to-market advantages, but integration cycles in semiconductor design are complex and can stretch across multiple years.

If uptake is strong, Marvell could consolidate its role as a preferred provider of interconnect technology in AI accelerators, positioning itself alongside NVIDIA, AMD, and custom silicon developers in hyperscale procurement strategies. Analysts also noted that Marvell’s holistic stack approach—providing not just PHY IP but also higher-layer integration—may help it capture more value from each design win.

However, competition is intensifying. Open standards like UCIe continue to evolve, and competitors from Intel to TSMC are investing heavily in chiplet integration. As a result, Marvell will likely need to keep innovating at pace to preserve its lead.